1. Field of the Invention
The present invention relates to a memory circuit suitable for use in a data delay circuit employed in a video system, and particularly to a memory circuit for reading data therefrom and writing the data therein within one address data period.
2. Description of the Related Art
A conventional memory circuit is provided with an I/O (input/output) circuit, an address counter, an address decoder and a memory array. Access to a memory in the conventional memory circuit is controlled by a control signal which is generated based on a master clock signal.
It is thus necessary to increase the frequency of the master clock signal in order to increase the speed of memory access. When a high frequency master clock signal is employed in the memory circuit, the power used up by the memory circuit increases and a high-speed type clock generator is also necessary.